diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2020-08-17 09:37:13 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-08-18 15:57:40 +0000 |
| commit | aa902036d0cc8dd48a36fd7cf5fd8e22930b7afd (patch) | |
| tree | 7166ac3a7f6aa8e2a56e97cca9e73e78859adeee /src/southbridge/intel/lynxpoint | |
| parent | 819d676fed535c80d68247ed938a6559ff1c7d10 (diff) | |
elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE
The wake source macro for GPE events was using 'GPIO'. However,
current usage is really all GPEs. Therefore, provide clarity
in the naming in order to allow for proper GPIO wake events
that are separate from the ACPI GPE block.
BUG=b:159947207
Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/elog.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 2e4df72658..8146794aa3 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -36,7 +36,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg, int start) for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } @@ -64,7 +64,7 @@ static void pch_log_gpe(void) gpe0_sts = inw(pmbase + GPE0_STS + 2) & gpe0_en; for (i = 0; i <= 15; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); } /* @@ -78,7 +78,7 @@ static void pch_log_gpe(void) if (!gpe0_high_gpios[i]) continue; if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, gpe0_high_gpios[i]); } } |