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authorWANG Siyuan <wangsiyuanbuaa@gmail.com>2015-06-08 10:13:13 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-06-23 01:10:52 +0200
commit6762a8b85e631c9076990021ac2392c5efcbda21 (patch)
treef85931952dc53bf6363357726fd12a8a8e03ad39 /src/southbridge/intel/lynxpoint
parent2dcd0fc4944c42d8dc012cd8be7b3c870dbd79c0 (diff)
AMD PI agesawrapper: add PSPP (PCIe Speed Power Policy) interface
PSPP policy is defined in 3rdparty/blobs/pi/amd/*/AGESA.h /// PCIe PSPP Power policy typedef enum { PsppDisabled, ///< PSPP disabled PsppPerformance = 1, ///< Performance PsppBalanceHigh, ///< Balance-High PsppBalanceLow, ///< Balance-Low PsppPowerSaving, ///< Power Saving MaxPspp ///< Max Pspp for boundary check } PCIE_PSPP_POLICY; Change-Id: I7fe735cddea94a83e38d856a3de1f27735467a28 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10461 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
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