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authorAaron Durbin <adurbin@chromium.org>2012-10-31 23:05:25 -0500
committerRonald G. Minnich <rminnich@gmail.com>2013-03-14 06:35:48 +0100
commit89f79a019fd049f26ed7bf40618ff960bd9e095e (patch)
treee3bf2a39fe6f4d9f2570a4373376aeefbf7a3664 /src/southbridge/intel/lynxpoint/spi.c
parentb9ea8b3fb0082840b0c9d449535f4c49c2e885ac (diff)
haswell: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2618 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/spi.c')
-rw-r--r--src/southbridge/intel/lynxpoint/spi.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/src/southbridge/intel/lynxpoint/spi.c b/src/southbridge/intel/lynxpoint/spi.c
index 8eea28c88f..ec7c862beb 100644
--- a/src/southbridge/intel/lynxpoint/spi.c
+++ b/src/southbridge/intel/lynxpoint/spi.c
@@ -35,19 +35,18 @@
#ifdef __SMM__
#include <arch/romcc_io.h>
-#include <northbridge/intel/haswell/pcie_config.c>
#define pci_read_config_byte(dev, reg, targ)\
- *(targ) = pcie_read_config8(dev, reg)
+ *(targ) = pci_read_config8(dev, reg)
#define pci_read_config_word(dev, reg, targ)\
- *(targ) = pcie_read_config16(dev, reg)
+ *(targ) = pci_read_config16(dev, reg)
#define pci_read_config_dword(dev, reg, targ)\
- *(targ) = pcie_read_config32(dev, reg)
+ *(targ) = pci_read_config32(dev, reg)
#define pci_write_config_byte(dev, reg, val)\
- pcie_write_config8(dev, reg, val)
+ pci_write_config8(dev, reg, val)
#define pci_write_config_word(dev, reg, val)\
- pcie_write_config16(dev, reg, val)
+ pci_write_config16(dev, reg, val)
#define pci_write_config_dword(dev, reg, val)\
- pcie_write_config32(dev, reg, val)
+ pci_write_config32(dev, reg, val)
#else /* !__SMM__ */
#include <device/device.h>
#include <device/pci.h>