haswell: Use SMM Modules

This commit adds support for using the SMM modules for haswell-based
boards. The SMI handling was also refactored to put the relocation
handler and permanent SMM handler loading in the cpu directory. All
tseg adjustment support is dropped by relying on the SMM module support
to perform the necessary relocations.

Change-Id: I8dd23610772fc4408567d9f4adf339596eac7b1f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2728
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 15 insertions, 81 deletions

diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index 0bb98813ed..80dea2ce5b 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -30,13 +30,6 @@
 #include <string.h>
 #include "pch.h"
 
-#if CONFIG_NORTHBRIDGE_INTEL_HASWELL
-#include "northbridge/intel/haswell/haswell.h"
-#endif
-
-extern unsigned char _binary_smm_start;
-extern unsigned char _binary_smm_size;
-
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value
  */
@@ -232,15 +225,17 @@ static void smi_set_eos(void)
 	outb(reg8, pmbase + SMI_EN);
 }
 
-extern uint8_t smm_relocation_start, smm_relocation_end;
-
-static void smm_relocate(void)
+void southbridge_smm_init(void)
 {
 	u32 smi_en;
 	u16 pm1_en;
 	u32 gpe0_en;
 
-	printk(BIOS_DEBUG, "Initializing SMM handler...");
+#if CONFIG_ELOG
+	/* Log events from chipset before clearing */
+	pch_log_state();
+#endif
+	printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
 
 	pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
 							PMBASE) & 0xff80;
@@ -253,10 +248,6 @@ static void smm_relocate(void)
 		return;
 	}
 
-	/* copy the SMM relocation code */
-	memcpy((void *)0x38000, &smm_relocation_start,
-			&smm_relocation_end - &smm_relocation_start);
-
 	printk(BIOS_DEBUG, "\n");
 	dump_smi_status(reset_smi_status());
 	dump_pm1_status(reset_pm1_status());
@@ -305,7 +296,10 @@ static void smm_relocate(void)
 	smi_en |= EOS | GBL_SMI_EN;
 
 	outl(smi_en, pmbase + SMI_EN);
+}
 
+void southbridge_trigger_smi(void)
+{
 	/**
 	 * There are several methods of raising a controlled SMI# via
 	 * software, among them:
@@ -324,78 +318,18 @@ static void smm_relocate(void)
 	outb(0x00, 0xb2);
 }
 
-static int smm_handler_copied = 0;
-
-static void smm_install(void)
-{
-	device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-	u32 smm_base = 0xa0000;
-	struct ied_header ied = {
-		.signature = "INTEL RSVD",
-		.size = IED_SIZE,
-		.reserved = {0},
-	};
-
-	/* The first CPU running this gets to copy the SMM handler. But not all
-	 * of them.
-	 */
-	if (smm_handler_copied)
-		return;
-	smm_handler_copied = 1;
-
-	/* enable the SMM memory window */
-	pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);
-
-#if CONFIG_SMM_TSEG
-	smm_base = pci_read_config32(dev, TSEG) & ~1;
-#endif
-
-	/* copy the real SMM handler */
-	printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base);
-	memcpy((void *)smm_base, &_binary_smm_start, (size_t)&_binary_smm_size);
-
-	/* copy the IED header into place */
-	if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) {
-		/* Top of TSEG region */
-		smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE;
-		printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n",
-		       smm_base);
-		memcpy((void *)smm_base, &ied, sizeof(ied));
-	}
-	wbinvd();
-
-	/* close the SMM memory window and enable normal SMM */
-	pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG);
-}
-
-void smm_init(void)
+void southbridge_clear_smi_status(void)
 {
-#if CONFIG_ELOG
-	/* Log events from chipset before clearing */
-	pch_log_state();
-#endif
-
-	/* Put SMM code to 0xa0000 */
-	smm_install();
+	/* Clear SMI status */
+	reset_smi_status();
 
-	/* Put relocation code to 0x38000 and relocate SMBASE */
-	smm_relocate();
+	/* Clear PM1 status */
+	reset_pm1_status();
 
-	/* We're done. Make sure SMIs can happen! */
+	/* Set EOS bit so other SMIs can occur. */
 	smi_set_eos();
 }
 
-void smm_lock(void)
-{
-	/* LOCK the SMM memory window and enable normal SMM.
-	 * After running this function, only a full reset can
-	 * make the SMM registers writable again.
-	 */
-	printk(BIOS_DEBUG, "Locking SMM.\n");
-	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
-			D_LCK | G_SMRAME | C_BASE_SEG);
-}
-
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
 {
 	/*