diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-12 17:01:31 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-08-06 23:26:15 +0000 |
commit | 16fe79048f5254661ff2342aa481cbb44657b7ff (patch) | |
tree | 5ad72bc5c5a97ca9a7a47f5ab24bbe622f12e9e9 /src/southbridge/intel/lynxpoint/smbus.c | |
parent | 12d010306b3892b01350e96d83275206215d9f31 (diff) |
sb/intel/*: Use common SMBus functions
All Intel southbridges implement the same SMBus functions.
This patch replaces all these similar and mostly identical
implementations with a common file.
This also makes i2c block read available to all those southbridges.
If the northbridge has to read a lot of SPD bytes sequentially, using
this function can reduce the time being spent to read SPD five-fold.
Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/smbus.c')
-rw-r--r-- | src/southbridge/intel/lynxpoint/smbus.c | 50 |
1 files changed, 1 insertions, 49 deletions
diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index d81a097fef..ccb5ea08f6 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -22,8 +22,8 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/io.h> +#include <southbridge/intel/common/smbus.h> #include "pch.h" -#include "smbus.h" static void pch_smbus_init(device_t dev) { @@ -54,54 +54,6 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int do_smbus_write_byte(unsigned smbus_base, unsigned device, - unsigned address, unsigned data) -{ - unsigned char global_status_register; - - if (smbus_wait_until_ready(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); - /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(data, smbus_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done(smbus_base) < 0) { - printk(BIOS_ERR, "SMBUS transaction timeout\n"); - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inb(smbus_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - if (global_status_register != (1 << 1)) { - printk(BIOS_ERR, "SMBUS transaction error\n"); - return SMBUS_ERROR; - } - - return 0; -} - static int lsmbus_write_byte(device_t dev, u8 address, u8 data) { u16 device; |