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authorElyes HAOUAS <ehaouas@noos.fr>2020-04-28 10:13:05 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 06:22:27 +0000
commit73ae076e954ea6acd2fd22386616cd4ce839c830 (patch)
treefe4dfa4a69391000f117a09bae8f2d5551e98758 /src/southbridge/intel/lynxpoint/serialio.c
parent8b6dfdeb203c5e10c804398b822f85df2b4b6d26 (diff)
sb/intel/lynxpoint: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I81b740e0cfcf0e1bf096427b45ffba06d357fee6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/serialio.c')
-rw-r--r--src/southbridge/intel/lynxpoint/serialio.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 4591566e1b..f789e7c784 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -134,14 +134,11 @@ static void serialio_init(struct device *dev)
struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
struct resource *bar0, *bar1;
int sio_index = -1;
- u32 reg32;
printk(BIOS_DEBUG, "Initializing Serial IO device\n");
/* Ensure memory and bus master are enabled */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Find BAR0 and BAR1 */
bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);