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authorAngel Pons <th3fanbus@gmail.com>2020-07-25 02:46:39 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-07-26 21:17:50 +0000
commit89739baf531e26dc81420df4f943bf8c163a0c0d (patch)
tree61b363d8d6681e93af4d65bf7f0fd0276fa4bc8c /src/southbridge/intel/lynxpoint/sata.c
parent4d2db06ab5f52bd283673c08b40b3b87600d0674 (diff)
{sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits
We have definitions for the bits in the PCI COMMAND register. Use them. Also add spaces around bitwise operators, to comply with the code style. Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/sata.c')
-rw-r--r--src/southbridge/intel/lynxpoint/sata.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 47e6f9be68..2f903f04fb 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -41,7 +41,8 @@ static void sata_init(struct device *dev)
/* SATA configuration */
/* Enable BARs */
- pci_write_config16(dev, PCI_COMMAND, 0x0007);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (config->ide_legacy_combined) {
printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");