diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2017-09-15 14:59:27 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-20 23:54:20 +0000 |
| commit | cfe7ad1e8f7ed6f3d72db2041bf2051ac88e2a5f (patch) | |
| tree | 4440a1f19698ac7b86aa16b129c0ead05ddfdd7a /src/southbridge/intel/lynxpoint/pmutil.c | |
| parent | b19e33f05ca43a40babe4f081bf6fb0ff53f5d4f (diff) | |
southbridge/intel/lynxpoint: refactor rtc failure checking
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: I368c31b9935c0fa9e8a1be416435dd76f44ec1ec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pmutil.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pmutil.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index b14c1f7c91..642d5befd0 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -553,3 +553,13 @@ void disable_gpe(u32 mask) gpe0_en &= ~mask; outl(gpe0_en, get_pmbase() + gpe0_reg); } + +int rtc_failure(void) +{ +#if defined(__SIMPLE_DEVICE__) + device_t dev = PCI_DEV(0, 31, 0); +#else + device_t dev = dev_find_slot(0, PCI_DEVFN(31, 0)); +#endif + return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); +} |