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| author | Elyes Haouas <ehaouas@noos.fr> | 2024-03-23 15:10:04 +0100 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-04-11 19:19:08 +0000 |
| commit | 31402178c56108e752b95c34562b6e3554a2c1d8 (patch) | |
| tree | 0ac4a3cea23ce5c66cc91f2883d3b30184d0f565 /src/southbridge/intel/lynxpoint/pcie.c | |
| parent | 1dc8f0272bd222125d2d26cfa2b311f3d134f6ca (diff) | |
tree: Remove blank lines before '}' and after '{'
Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pcie.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 7d31b3ea18..7f5e1face6 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -231,7 +231,6 @@ static void pcie_enable_clock_gating(void) rp = root_port_number(dev); if (!is_rp_enabled(rp)) { - /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) pci_or_config8(dev, 0xe1, 0x3c); |