diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-12-17 11:31:40 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-14 18:25:10 +0100 |
| commit | 74c0d05cf51e089357712b2c855f344caba680fb (patch) | |
| tree | 81ff5169a3b42ea32207ec783485508e1174f7ac /src/southbridge/intel/lynxpoint/pcie.c | |
| parent | 045f153a4fe2b6e1cb193db01866218d0316f253 (diff) | |
lynxpoint: Update device IDs and clock gating setup
- Add device IDs for lynxpoint mobile and LP variants.
- Update the clock gating setup based on BWG
- Update the SATA programming based on BWG
- Add a DEVSLP0 mux config register
Change-Id: Icf4d7bab7f3df7adef5eb7c5e310a6995227a0e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2649
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pcie.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 80cd3550e1..9463d0cb00 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -260,11 +260,13 @@ static struct device_operations device_ops = { .ops_pci = &pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16, - 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, - 0x1e10, 0x1e12, 0x1e14, 0x1e16, - 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, - 0 }; +static const unsigned short pci_device_ids[] = { + /* Lynxpoint Mobile */ + 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e, + /* Lynxpoint Low Power */ + 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a, + 0 +}; static const struct pci_driver pch_pcie __pci_driver = { .ops = &device_ops, |