diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-28 10:13:05 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 06:22:27 +0000 |
| commit | 73ae076e954ea6acd2fd22386616cd4ce839c830 (patch) | |
| tree | fe4dfa4a69391000f117a09bae8f2d5551e98758 /src/southbridge/intel/lynxpoint/pcie.c | |
| parent | 8b6dfdeb203c5e10c804398b822f85df2b4b6d26 (diff) | |
sb/intel/lynxpoint: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I81b740e0cfcf0e1bf096427b45ffba06d357fee6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pcie.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 0ca49b802c..3daf1826a5 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -277,7 +277,7 @@ static void root_port_commit_config(void) for (i = 0; i < rpc.num_ports; i++) { struct device *dev; - u32 reg32; + u16 reg16; dev = rpc.ports[i]; @@ -292,10 +292,9 @@ static void root_port_commit_config(void) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device if possible */ pch_disable_devfn(dev); @@ -654,19 +653,14 @@ static void pch_pcie_early(struct device *dev) static void pci_init(struct device *dev) { u16 reg16; - u32 reg32; printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it |