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| author | Shuo Liu <shuo.liu@intel.com> | 2024-10-09 04:59:07 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-10-14 15:28:09 +0000 |
| commit | edf390dee50d52cb31f908b2e7959acf2fff54e2 (patch) | |
| tree | 3f3cead93a54edfc863b17af789c1fc4cd0cbc1f /src/southbridge/intel/lynxpoint/pcie.c | |
| parent | 85541960df2c34d0e7c621cc1cfb3c169439d9d0 (diff) | |
Documentation/soc/intel/xeon_sp: Add targeted feature list
Add targeted feature list for Xeon 6 coreboot. The listed features
are targeted to be supported by Xeon 6 coreboot design, while some
specific items might need fixes and improvements per community
feedback.
Change-Id: Ibecd63dfca10712223ccdd943109ba28ed668200
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84701
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pcie.c')
0 files changed, 0 insertions, 0 deletions