summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/lynxpoint/pch.h
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-09-02 20:19:15 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-09-14 07:07:04 +0000
commitd9f1b04ec5f87c05da60c5da84df35624ecd0fac (patch)
tree877718f211e7540f2899bfd3f537481c43cdd363 /src/southbridge/intel/lynxpoint/pch.h
parent78c615c332859e1d59924214100b6da506131d48 (diff)
sb/intel/lynxpoint: Do not determine PCH type at runtime
Both PCH types are very different, and mixing the code for both together isn't useful. First of all, inline `pch_is_lp` to return a constant. This allows the compiler to optimize out unused code, which results in smaller executables. For the Asrock B85M Pro4, it's about 2.5 KiB less. Subsequent commits will further split the southbridge code. Change-Id: Iba904acf64096478d1b76ffd05a076f0203502f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45047 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 2c86ff0ab6..1ecad62796 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -69,6 +69,11 @@
#ifndef __ACPI__
+static inline int pch_is_lp(void)
+{
+ return CONFIG(INTEL_LYNXPOINT_LP);
+}
+
/* PCH platform types, safe for MRC consumption */
enum pch_platform_type {
PCH_TYPE_MOBILE = 0,
@@ -84,7 +89,6 @@ void usb_xhci_route_all(void);
enum pch_platform_type get_pch_platform_type(void);
int pch_silicon_revision(void);
int pch_silicon_id(void);
-int pch_is_lp(void);
u16 get_pmbase(void);
u16 get_gpiobase(void);