diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-24 12:20:28 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-31 10:08:35 +0000 |
| commit | 8963f7d40be4961e8ae6dca4185e4e682ba2fdb9 (patch) | |
| tree | 02f2ce901e111c264ecd4744dad18c0883251ca5 /src/southbridge/intel/lynxpoint/pch.h | |
| parent | 2d35cf8689998b9dc0626083c3a3d867f82a35e0 (diff) | |
sb/intel/lynxpoint: Drop unnecessary `UL` suffix
With BUILD_TIMELESS=1, Asrock B85M Pro4 and Google Wolf do not change.
Change-Id: I9ba4097cd82c4ff68315a40e1e955e4ed9a43862
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46719
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 50e0b142af..66cd05e66a 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -167,7 +167,7 @@ void mainboard_config_rcba(void); #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 #define PMIR 0xac -#define PMIR_CF9LOCK (1UL << 31) +#define PMIR_CF9LOCK (1 << 31) #define PMIR_CF9GR (1 << 20) /* GEN_PMCON_3 bits */ @@ -315,7 +315,7 @@ void mainboard_config_rcba(void); #define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ #define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ #define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ -#define XHCI_USB3_PORTSC_WPR (1UL << 31) /* Warm Port Reset */ +#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ #define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ #define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ #define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ @@ -408,7 +408,7 @@ void mainboard_config_rcba(void); #define RPFN 0x0404 /* 32bit */ /* Root Port configuratinon space hide */ -#define RPFN_HIDE(port) (1UL << (((port) * 4) + 3)) +#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) /* Get the function number assigned to a Root Port */ #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) /* Set the function number for a Root Port */ |