diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-03-04 01:44:15 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-08 19:14:17 +0000 |
| commit | a51e379eaff3652dc64e23bb0d3784222a38723a (patch) | |
| tree | 5296bfb357dddedc61f585f3bf36c14b351b6044 /src/southbridge/intel/lynxpoint/pch.h | |
| parent | 8a6377ec24c85bc6a18eb9c57045746d2261ce1a (diff) | |
nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APIC
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers and reserved from the OS.
GFXVTBAR/VTVC0BAR policy registers set to be consistent with
proprietary vendor firmwares on hardware of same platform
(2 different vendor firmwares compared, found to be identical).
Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24983
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index af9e9542b5..f14a339d7b 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -282,6 +282,8 @@ void pch_enable_lpc(void); #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ +#define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */ +#define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */ #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ @@ -670,6 +672,11 @@ void pch_enable_lpc(void); #define PCH_DISABLE_MEI1 (1 << 1) #define PCH_ENABLE_DBDF (1 << 0) +#define PCH_IOAPIC_PCI_BUS 250 +#define PCH_IOAPIC_PCI_SLOT 31 +#define PCH_HPET_PCI_BUS 250 +#define PCH_HPET_PCI_SLOT 15 + /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) |