diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-04-18 23:57:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-09 05:21:23 +0000 |
| commit | aced1f02cf24be5a56a97b75c98c861e57e14595 (patch) | |
| tree | 20aaa49f8823cd571888b509132deb5d67ede337 /src/southbridge/intel/lynxpoint/pch.h | |
| parent | fc096888e17c2925955bff601b2baddb3b630373 (diff) | |
sb/intel/lynxpoint: Add SerialIO UART console support
Derived from Broadwell and adapted to follow what soc/intel does. Note
that SERIALIO_UART_CONSOLE is meant to be selected from the mainboards
which expose a SerialIO UART. UART_FOR_CONSOLE also needs to be set in
mainboard Kconfig accordingly.
It is possible that some of the UART configuration steps in bootblock
are unnecessary. However, some of the steps turn off power management
features and others are undocumented: omitting them could cause weird
issues.
Finally, add a config file to ensure the code gets build-tested.
Tested on out-of-tree Compal LA-A992P, SerialIO UART 0 can be used to
receive coreboot and SeaBIOS logs.
Change-Id: Ifb3460dd50ed03421a38f03c80f91ae9fd604022
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52489
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7b09d54f18..598c2dc7b2 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -157,6 +157,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void enable_usb_bar(void); void early_pch_init(void); void pch_enable_lpc(void); +void uart_bootblock_init(void); void mainboard_config_superio(void); void mainboard_config_rcba(void); @@ -372,6 +373,9 @@ void mainboard_config_rcba(void); #define SIO_REG_PPR_CLOCK 0x800 #define SIO_REG_PPR_CLOCK_EN (1 << 0) +#define SIO_REG_PPR_CLOCK_UPDATE (1 << 31) +#define SIO_REG_PPR_CLOCK_M_DIV 0x25a +#define SIO_REG_PPR_CLOCK_N_DIV 0x7fff #define SIO_REG_PPR_RST 0x804 #define SIO_REG_PPR_RST_ASSERT 0x3 #define SIO_REG_PPR_GEN 0x808 |