diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-04-24 11:54:01 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-26 08:26:56 +0000 |
| commit | 35605d689a50e8ed0ce707171acf3bb69c024b7c (patch) | |
| tree | fdf42f67fa4e4d01cb7279f927d3a49feffcb12a /src/southbridge/intel/lynxpoint/pch.h | |
| parent | babbe08e7c787939b6e5530186e9a92795b42ae3 (diff) | |
sb/intel/lynxpoint: Add and use power state bit macros
Tested with BUILD_TIMELESS=1, Google Wolf remains identical.
Change-Id: Id85b76c0aaf481f99f55a9ce6d813ff32753e588
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 955eb7249f..763a6ca2a6 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -204,8 +204,18 @@ void mainboard_config_rcba(void); #define SERIRQ_CNTL 0x64 #define GEN_PMCON_1 0xa0 +#define SMI_LOCK (1 << 4) #define GEN_PMCON_2 0xa2 +#define SYSTEM_RESET_STS (1 << 4) +#define THERMTRIP_STS (1 << 3) +#define SYSPWR_FLR (1 << 1) +#define PWROK_FLR (1 << 0) #define GEN_PMCON_3 0xa4 +#define SUS_PWR_FLR (1 << 14) +#define GEN_RST_STS (1 << 9) +#define RTC_BATTERY_DEAD (1 << 2) +#define PWR_FLR (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) #define PMIR 0xac #define PMIR_CF9LOCK (1 << 31) #define PMIR_CF9GR (1 << 20) @@ -615,6 +625,7 @@ void mainboard_config_rcba(void); #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 +#define SECOND_TO_STS (1 << 1) #define ALT_GP_SMI_EN2 0x5c #define ALT_GP_SMI_STS2 0x5e |