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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-18 16:33:39 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-21 07:00:45 +0000 |
| commit | 12b121cdb450d96309dd96b2ccc25fc5501d2250 (patch) | |
| tree | 1d94c123c23512b811d69d9876ac9a860bbbe0f6 /src/southbridge/intel/lynxpoint/pch.h | |
| parent | 544b572c07bb09aba36705b5d8ffca3b793323f6 (diff) | |
southbridge/intel: Tidy up preprocessor and headers
Change-Id: I52a7b39566acd64ac21a345046675e05649a40f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34980
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 18 |
1 files changed, 5 insertions, 13 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 540a4d3574..3f37887567 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -88,13 +88,10 @@ #ifndef __ACPI__ -#if defined(__SMM__) && !defined(__ASSEMBLER__) void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); void usb_ehci_disable(pci_devfn_t dev); void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); void usb_xhci_route_all(void); -#endif - /* State Machine configuration. */ #define RCBA_REG_SIZE_MASK 0x8000 @@ -135,7 +132,6 @@ struct rcba_config_instruction u32 or_value; }; -#if !defined(__ASSEMBLER__) void pch_config_rcba(const struct rcba_config_instruction *rcba_config); int pch_silicon_revision(void); int pch_silicon_id(void); @@ -169,30 +165,26 @@ void disable_all_gpe(void); void enable_gpe(u32 mask); void disable_gpe(u32 mask); -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include <device/device.h> -#include "chip.h" void pch_enable(struct device *dev); void pch_disable_devfn(struct device *dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG(ELOG) void pch_log_state(void); -#endif void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -#else void enable_smbus(void); -void enable_usb_bar(void); + +#if ENV_ROMSTAGE int smbus_read_byte(unsigned device, unsigned address); +#endif + +void enable_usb_bar(void); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); void mainboard_config_superio(void); -#endif /* !__PRE_RAM__ && !__SMM__ */ -#endif /* __ASSEMBLER__ */ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 |