diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-12-19 09:12:31 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 20:16:26 +0100 |
| commit | 26e7dd703dea8dce30829d8bb73c1f27a2178d72 (patch) | |
| tree | 924161b457fd106535444b45089d3e0ede1dd8d9 /src/southbridge/intel/lynxpoint/pch.h | |
| parent | eb58bc5af6b8bf626f38d0c07bf55db2835f53b5 (diff) | |
haswell: more ULT/LP support and minor tweaks
- Add ME device ID for Lynxpoint LP
- Add GPU device IDs for ULT
- SATA init tweaks from checking against DXE reference code
- Remove the ICH7 from the SPI driver so it works on all lynxpoint
without having to add more LPC device ID checks
- Add function disable for audio dsp and xhci, remove PCI bridge
- Add interrupt route registers for new devices (needs romstage setup)
Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2680
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index f6707f7bdb..5a3725ef29 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -407,6 +407,8 @@ unsigned get_gpios(const int *gpio_num_array); #define D22IP_IDERIP 8 /* IDE-R Pin */ #define D22IP_MEI2IP 4 /* MEI #2 Pin */ #define D22IP_MEI1IP 0 /* MEI #1 Pin */ +#define D20IP 0x3128 /* 32bit */ +#define D20IP_XHCI 0 /* XHCI Pin */ #define D31IR 0x3140 /* 16bit */ #define D30IR 0x3142 /* 16bit */ #define D29IR 0x3144 /* 16bit */ @@ -414,7 +416,11 @@ unsigned get_gpios(const int *gpio_num_array); #define D27IR 0x3148 /* 16bit */ #define D26IR 0x314c /* 16bit */ #define D25IR 0x3150 /* 16bit */ +#define D23IR 0x3158 /* 16bit */ #define D22IR 0x315c /* 16bit */ +#define D20IR 0x3160 /* 16bit */ +#define D21IR 0x3164 /* 16bit */ +#define D19IR 0x3168 /* 16bit */ #define OIC 0x31fe /* 16bit */ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 @@ -434,8 +440,8 @@ unsigned get_gpios(const int *gpio_num_array); #define CG 0x341c /* 32bit */ /* Function Disable 1 RCBA 0x3418 */ -#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)|(1 << 27)) -#define PCH_DISABLE_P2P (1 << 1) +#define PCH_DISABLE_ALWAYS (1 << 0) +#define PCH_DISABLE_ADSPD (1 << 1) #define PCH_DISABLE_SATA1 (1 << 2) #define PCH_DISABLE_SMBUS (1 << 3) #define PCH_DISABLE_HD_AUDIO (1 << 4) @@ -445,6 +451,7 @@ unsigned get_gpios(const int *gpio_num_array); #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) #define PCH_DISABLE_THERMAL (1 << 24) #define PCH_DISABLE_SATA2 (1 << 25) +#define PCH_DISABLE_XHCI (1 << 27) /* Function Disable 2 RCBA 0x3428 */ #define PCH_DISABLE_KT (1 << 4) |