diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-24 12:20:28 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-31 10:08:35 +0000 |
| commit | 8963f7d40be4961e8ae6dca4185e4e682ba2fdb9 (patch) | |
| tree | 02f2ce901e111c264ecd4744dad18c0883251ca5 /src/southbridge/intel/lynxpoint/pch.c | |
| parent | 2d35cf8689998b9dc0626083c3a3d867f82a35e0 (diff) | |
sb/intel/lynxpoint: Drop unnecessary `UL` suffix
With BUILD_TIMELESS=1, Asrock B85M Pro4 and Google Wolf do not change.
Change-Id: I9ba4097cd82c4ff68315a40e1e955e4ed9a43862
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46719
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index adc011bb7b..1a338b14ec 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -97,31 +97,31 @@ void pch_disable_devfn(struct device *dev) break; case PCI_DEVFN(21, 0): /* DMA */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 1): /* I2C0 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 2): /* I2C1 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 3): /* SPI0 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 4): /* SPI1 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 5): /* UART0 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 6): /* UART1 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(22, 0): /* MEI #1 */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -137,7 +137,7 @@ void pch_disable_devfn(struct device *dev) break; case PCI_DEVFN(23, 0): /* SDIO */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ RCBA32_OR(BUC, PCH_DISABLE_GBE); |