diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-02-25 10:51:52 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-21 23:03:27 +0100 |
| commit | b37d1fb95ae810bf8f55cc30aa6a5ca921c1ca05 (patch) | |
| tree | 8ce1acf08f8339cdb39ae681b5a52d06be88ebee /src/southbridge/intel/lynxpoint/me_9.x.c | |
| parent | b86113fd9ade587f7cb69b8c0c5d6407917fb185 (diff) | |
lynxpoint: update MBP give up routine
I'm not sure if I screwed this up originally or the Intel docs changed
(I didn't bother to go back and check). According to ME BWG 1.1.0 the give
up bit is in the host general status #2 register.
Change-Id: Ieaaf524b93e9eb9806173121dda63d0133278c2d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2808
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/me_9.x.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/me_9.x.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 63b520531b..2e790fc2a5 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -804,7 +804,7 @@ static void intel_me_mbp_give_up(device_t dev) struct mei_csr csr; reg32 = PCI_ME_MBP_GIVE_UP; - pci_write_config32(dev, PCI_ME_H_GS3, reg32); + pci_write_config32(dev, PCI_ME_H_GS2, reg32); read_host_csr(&csr); csr.reset = 1; csr.interrupt_generate = 1; |