diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-05-24 11:06:49 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-25 23:38:36 +0100 |
| commit | c593999a0ad9b9f19c8171f6229faa191d055491 (patch) | |
| tree | 0759809b866a346d98870803a6ad5aceb4905149 /src/southbridge/intel/lynxpoint/lpc.c | |
| parent | 7820c77f2c118d604d0acfce8deb40536cae3121 (diff) | |
lynxpoint: Enable extra 16 IOAPIC entries for GPIO PIRQ
LynxPoint-LP has an additional 16 entries in the IOAPIC that
can be assigned to specific GPIOs when they are configured
as PIRQ.
The maximum redirection entries field in the IOAPIC needs to
be set to 0x27 when this is enabled.
Additionally specific GPIOs need to be routed to PIRQ so they
interrupt via the IOAPIC instead of the GPIO IRQ 14/15.
Change-Id: Ie587e1d203422ff6fb7fc5056d20a5ae66720991
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56620
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4203
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/lpc.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 33d74f1903..ff50476a62 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -59,6 +59,11 @@ static void pch_enable_ioapic(struct device *dev) /* affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + if (pch_is_lp()) { + /* PCH-LP has 39 redirection entries */ + reg32 &= ~0x00ff0000; + reg32 |= 0x00270000; + } io_apic_write(IO_APIC_ADDR, 0x01, reg32); /* |