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authorDuncan Laurie <dlaurie@chromium.org>2013-05-14 11:16:34 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-11-25 23:27:53 +0100
commit8d783b84930e2e14e4f70234ea6589acd06557e7 (patch)
treed8aaf94f486d2935eb86cfacfa397fe16fa8a639 /src/southbridge/intel/lynxpoint/lpc.c
parent1c0540000dc4705cee44857293285382f4ae8bad (diff)
slippy: Minor vboot related fixes
- Disable EC software sync for now - Report correct EC active firmware mode - Force enable developer mode by default - Set up PCH generic decode regions in romstage - Pass the oprom_is_loaded flag into vboot handoff data Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51155 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4169 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/lpc.c')
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c20
1 files changed, 1 insertions, 19 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index c3b5322190..33d74f1903 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -520,18 +520,6 @@ static void pch_fixups(struct device *dev)
RCBA32_OR(0x21a8, 0x3);
}
-static void pch_decode_init(struct device *dev)
-{
- config_t *config = dev->chip_info;
-
- printk(BIOS_DEBUG, "pch_decode_init\n");
-
- pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec);
- pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec);
- pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec);
- pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec);
-}
-
static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "pch: lpc_init\n");
@@ -712,12 +700,6 @@ static void pch_lpc_read_resources(device_t dev)
memset(gnvs, 0, sizeof(global_nvs_t));
}
-static void pch_lpc_enable_resources(device_t dev)
-{
- pch_decode_init(dev);
- return pci_dev_enable_resources(dev);
-}
-
static void pch_lpc_enable(device_t dev)
{
/* Enable PCH Display Port */
@@ -745,7 +727,7 @@ static struct pci_operations pci_ops = {
static struct device_operations device_ops = {
.read_resources = pch_lpc_read_resources,
.set_resources = pci_dev_set_resources,
- .enable_resources = pch_lpc_enable_resources,
+ .enable_resources = pci_dev_enable_resources,
.init = lpc_init,
.enable = pch_lpc_enable,
.scan_bus = scan_static_bus,