diff options
| author | Martin Roth <martinroth@google.com> | 2017-06-24 21:29:38 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-16 19:22:18 +0000 |
| commit | 7a1a3ad2ce3403f0379b72d30360e2bed02e9c26 (patch) | |
| tree | 0db32f6a8f2349b5ce269996f3246b13fec9d5af /src/southbridge/intel/lynxpoint/lpc.c | |
| parent | 9fa8ebe1a41fab33badfa4745708e1ad237e8a34 (diff) | |
southbridge/intel: add IS_ENABLED() around Kconfig symbol references
Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/lpc.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ff78ea9eeb..b43ca329b6 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -77,7 +77,7 @@ static void pch_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -292,7 +292,7 @@ static void pch_rtc_init(struct device *dev) if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); #endif } @@ -498,7 +498,7 @@ static void enable_lp_clock_gating(device_t dev) static void pch_set_acpi_mode(void) { -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -760,7 +760,7 @@ static void southbridge_inject_dsdt(device_t dev) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) chromeos_init_vboot(&(gnvs->chromeos)); #endif |