sb/intel/lynxpoint: Program PM registers directly

Perform the same operations as the RCBA reg script did, but directly
writing the corresponding registers. Some of these operations could be
simplified, but it is not done on this commit to ease verification.

Change-Id: I4c3177ab14ca9bfa2e8d11c27fb249850183eee5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>

1 files changed, 45 insertions, 50 deletions

diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index f486434045..26bd30ffe6 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -276,55 +276,6 @@ static void lpt_pm_init(struct device *dev)
 	printk(BIOS_DEBUG, "LynxPoint PM init\n");
 }
 
-const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
-	RCBA_RMW_REG_32(0x232c, ~1, 0x00000000),
-	RCBA_RMW_REG_32(0x1100, ~0xc000, 0xc000),
-	RCBA_RMW_REG_32(0x1100, ~0, 0x00000100),
-	RCBA_RMW_REG_32(0x1100, ~0, 0x0000003f),
-	RCBA_RMW_REG_32(0x2320, ~0x60, 0x10),
-	RCBA_RMW_REG_32(0x3314,  0, 0x00012fff),
-	RCBA_RMW_REG_32(0x3318,  0, 0x0dcf0400),
-	RCBA_RMW_REG_32(0x3324,  0, 0x04000000),
-	RCBA_RMW_REG_32(0x3368,  0, 0x00041400),
-	RCBA_RMW_REG_32(0x3388,  0, 0x3f8ddbff),
-	RCBA_RMW_REG_32(0x33ac,  0, 0x00007001),
-	RCBA_RMW_REG_32(0x33b0,  0, 0x00181900),
-	RCBA_RMW_REG_32(0x33c0,  0, 0x00060A00),
-	RCBA_RMW_REG_32(0x33d0,  0, 0x06200840),
-	RCBA_RMW_REG_32(0x3a28,  0, 0x01010101),
-	RCBA_RMW_REG_32(0x3a2c,  0, 0x04040404),
-	RCBA_RMW_REG_32(0x2b1c,  0, 0x03808033),
-	RCBA_RMW_REG_32(0x2b34,  0, 0x80000009),
-	RCBA_RMW_REG_32(0x3348,  0, 0x022ddfff),
-	RCBA_RMW_REG_32(0x334c,  0, 0x00000001),
-	RCBA_RMW_REG_32(0x3358,  0, 0x0001c000),
-	RCBA_RMW_REG_32(0x3380,  0, 0x3f8ddbff),
-	RCBA_RMW_REG_32(0x3384,  0, 0x0001c7e1),
-	RCBA_RMW_REG_32(0x338c,  0, 0x0001c7e1),
-	RCBA_RMW_REG_32(0x3398,  0, 0x0001c000),
-	RCBA_RMW_REG_32(0x33a8,  0, 0x00181900),
-	RCBA_RMW_REG_32(0x33dc,  0, 0x00080000),
-	RCBA_RMW_REG_32(0x33e0,  0, 0x00000001),
-	RCBA_RMW_REG_32(0x3a20,  0, 0x00000404),
-	RCBA_RMW_REG_32(0x3a24,  0, 0x01010101),
-	RCBA_RMW_REG_32(0x3a30,  0, 0x01010101),
-	RCBA_RMW_REG_32(0x0410, ~0, 0x00000003),
-	RCBA_RMW_REG_32(0x2618, ~0, 0x08000000),
-	RCBA_RMW_REG_32(0x2300, ~0, 0x00000002),
-	RCBA_RMW_REG_32(0x2600, ~0, 0x00000008),
-	RCBA_RMW_REG_32(0x33b4,  0, 0x00007001),
-	RCBA_RMW_REG_32(0x3350,  0, 0x022ddfff),
-	RCBA_RMW_REG_32(0x3354,  0, 0x00000001),
-	RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000),  /* Power Optimizer */
-	RCBA_RMW_REG_32(0x33c8, ~0, 0x00000080),  /* Power Optimizer */
-	RCBA_RMW_REG_32(0x2b10,  0, 0x0000883c),  /* Power Optimizer */
-	RCBA_RMW_REG_32(0x2b14,  0, 0x1e0a4616),  /* Power Optimizer */
-	RCBA_RMW_REG_32(0x2b24,  0, 0x40000005),  /* Power Optimizer */
-	RCBA_RMW_REG_32(0x2b20,  0, 0x0005db01),  /* Power Optimizer */
-	RCBA_RMW_REG_32(0x3a80,  0, 0x05145005),
-	RCBA_END_CONFIG
-};
-
 /* LynxPoint LP PCH Power Management init */
 static void lpt_lp_pm_init(struct device *dev)
 {
@@ -335,7 +286,51 @@ static void lpt_lp_pm_init(struct device *dev)
 
 	pci_write_config8(dev, 0xa9, 0x46);
 
-	pch_config_rcba(lpt_lp_pm_rcba);
+	RCBA32_AND_OR(0x232c, ~1, 0x00000000);
+	RCBA32_AND_OR(0x1100, ~0xc000, 0xc000);
+	RCBA32_AND_OR(0x1100, ~0, 0x00000100);
+	RCBA32_AND_OR(0x1100, ~0, 0x0000003f);
+	RCBA32_AND_OR(0x2320, ~0x60, 0x10);
+	RCBA32_AND_OR(0x3314,  0, 0x00012fff);
+	RCBA32_AND_OR(0x3318,  0, 0x0dcf0400);
+	RCBA32_AND_OR(0x3324,  0, 0x04000000);
+	RCBA32_AND_OR(0x3368,  0, 0x00041400);
+	RCBA32_AND_OR(0x3388,  0, 0x3f8ddbff);
+	RCBA32_AND_OR(0x33ac,  0, 0x00007001);
+	RCBA32_AND_OR(0x33b0,  0, 0x00181900);
+	RCBA32_AND_OR(0x33c0,  0, 0x00060A00);
+	RCBA32_AND_OR(0x33d0,  0, 0x06200840);
+	RCBA32_AND_OR(0x3a28,  0, 0x01010101);
+	RCBA32_AND_OR(0x3a2c,  0, 0x04040404);
+	RCBA32_AND_OR(0x2b1c,  0, 0x03808033);
+	RCBA32_AND_OR(0x2b34,  0, 0x80000009);
+	RCBA32_AND_OR(0x3348,  0, 0x022ddfff);
+	RCBA32_AND_OR(0x334c,  0, 0x00000001);
+	RCBA32_AND_OR(0x3358,  0, 0x0001c000);
+	RCBA32_AND_OR(0x3380,  0, 0x3f8ddbff);
+	RCBA32_AND_OR(0x3384,  0, 0x0001c7e1);
+	RCBA32_AND_OR(0x338c,  0, 0x0001c7e1);
+	RCBA32_AND_OR(0x3398,  0, 0x0001c000);
+	RCBA32_AND_OR(0x33a8,  0, 0x00181900);
+	RCBA32_AND_OR(0x33dc,  0, 0x00080000);
+	RCBA32_AND_OR(0x33e0,  0, 0x00000001);
+	RCBA32_AND_OR(0x3a20,  0, 0x00000404);
+	RCBA32_AND_OR(0x3a24,  0, 0x01010101);
+	RCBA32_AND_OR(0x3a30,  0, 0x01010101);
+	RCBA32_AND_OR(0x0410, ~0, 0x00000003);
+	RCBA32_AND_OR(0x2618, ~0, 0x08000000);
+	RCBA32_AND_OR(0x2300, ~0, 0x00000002);
+	RCBA32_AND_OR(0x2600, ~0, 0x00000008);
+	RCBA32_AND_OR(0x33b4,  0, 0x00007001);
+	RCBA32_AND_OR(0x3350,  0, 0x022ddfff);
+	RCBA32_AND_OR(0x3354,  0, 0x00000001);
+	RCBA32_AND_OR(0x33d4, ~0, 0x08000000); /* Power Optimizer */
+	RCBA32_AND_OR(0x33c8, ~0, 0x00000080); /* Power Optimizer */
+	RCBA32_AND_OR(0x2b10,  0, 0x0000883c); /* Power Optimizer */
+	RCBA32_AND_OR(0x2b14,  0, 0x1e0a4616); /* Power Optimizer */
+	RCBA32_AND_OR(0x2b24,  0, 0x40000005); /* Power Optimizer */
+	RCBA32_AND_OR(0x2b20,  0, 0x0005db01); /* Power Optimizer */
+	RCBA32_AND_OR(0x3a80,  0, 0x05145005);
 
 	pci_write_config32(dev, 0xac,
 		pci_read_config32(dev, 0xac) | (1 << 21));