diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-03-08 17:00:37 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-21 23:11:25 +0100 |
| commit | 467f31de92ca2ed9df1530270e9aabdd69fe8f88 (patch) | |
| tree | 61092ad464c81d2f69cc66fc27e2db1ccb2df710 /src/southbridge/intel/lynxpoint/lpc.c | |
| parent | 7922b468b51eea58c7238f11b21820b8d3747d6b (diff) | |
haswell/lynxpoint: Use new PCH/PM helper functions
This makes use of the new functions from pmutil.c that take
care of the differences between -H and -LP chipsets.
It also adds support for the LynxPoint-LP GPE0 register block
and the SMI/SCI routing differences.
The FADT is updated to report the new 256 byte GPE0 block on
wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address
block so that part is zeroed to prevent IASL and the kernel
from complaining about a mismatch.
This was tested on WTM2. Unfortunately I am still unable to get an
SCI delivered from the EC but I suspect that is due to a magic
command needed to put the EC in ACPI mode. Instead I verified that
all of the power management and GPIO registers were set to expected
values.
I also tested transitions into S3 and S5 from both the kernel and
by pressing the power button at the developer mode screen and they
all function as expected.
Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2816
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/lpc.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 89d7350364..a943ca704b 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -184,12 +185,12 @@ static void pch_gpi_routing(device_t dev) static void pch_power_options(device_t dev) { u8 reg8; - u16 reg16, pmbase; + u16 reg16; u32 reg32; const char *state; /* Get the chip configuration */ config_t *config = dev->chip_info; - + u16 pmbase = get_pmbase(); int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; int nmi_option; @@ -257,13 +258,19 @@ static void pch_power_options(device_t dev) reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME pci_write_config16(dev, GEN_PMCON_1, reg16); - // Set the board's GPI routing. - pch_gpi_routing(dev); + /* + * Set the board's GPI routing on LynxPoint-H. + * This is done as part of GPIO configuration on LynxPoint-LP. + */ + if (pch_is_lp()) + pch_gpi_routing(dev); - pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + /* GPE setup based on device tree configuration */ + enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, + config->gpe0_en_3, config->gpe0_en_4); - outl(config->gpe0_en, pmbase + GPE0_EN); - outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); + /* SMI setup based on device tree configuration */ + enable_alt_smi(config->alt_gp_smi_en); /* Set up power management block and determine sleep mode */ reg32 = inl(pmbase + 0x04); // PM1_CNT |