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authorStefan Reinauer <reinauer@chromium.org>2013-12-03 12:13:26 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-12-05 20:13:08 +0100
commitab365af0a05e391d1e20e39e8bfb61c023b0a678 (patch)
treecf9400d95ea9ba7f8412751cdd398ca5d3ff1017 /src/southbridge/intel/lynxpoint/lp_gpio.c
parentc0254e6b6fbe7268fa47b2d4bd0a203423b2eec2 (diff)
lynxpoint: implement additional programming steps
The BIOS spec for LynxPoint calls out additional programming steps for the PCIe Root Ports. Implement those steps from the BIOS spec. These steps are completed before deeper PCIe probing. The "late" programming was removed as that was applicable to Cougar/Panther point where this code was originally copied, though there was some overlap. Change-Id: I64f25e4451e035d98ca6b66b0335bd280b70b074 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59558 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4323 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/lp_gpio.c')
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