diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2012-10-31 23:05:25 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 06:35:48 +0100 |
| commit | 89f79a019fd049f26ed7bf40618ff960bd9e095e (patch) | |
| tree | e3bf2a39fe6f4d9f2570a4373376aeefbf7a3664 /src/southbridge/intel/lynxpoint/finalize.c | |
| parent | b9ea8b3fb0082840b0c9d449535f4c49c2e885ac (diff) | |
haswell: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2618
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/finalize.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/finalize.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c index 796633d024..2cece13e17 100644 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ b/src/southbridge/intel/lynxpoint/finalize.c @@ -21,7 +21,6 @@ #include <arch/io.h> #include <arch/romcc_io.h> #include <console/post_codes.h> -#include <northbridge/intel/haswell/pcie_config.c> #include <spi-generic.h> #include "pch.h" @@ -51,15 +50,15 @@ void intel_pch_finalize_smm(void) RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ - pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); /* GEN_PMCON Lock */ - pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); - pcie_write_config32(PCI_DEV(0, 27, 0), 0x74, - pcie_read_config32(PCI_DEV(0, 27, 0), 0x74)); + pci_write_config32(PCI_DEV(0, 27, 0), 0x74, + pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); |