diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-24 11:53:47 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-24 20:43:15 +0000 |
| commit | 84fa224b53b726bec2a75dfdedd234bf60b0246e (patch) | |
| tree | bff11a3c6904b618407b9f48ef11ee28310d101f /src/southbridge/intel/lynxpoint/early_pch.c | |
| parent | 2f30e8ca03602c14fd98527f1ea54d2a80e4fd63 (diff) | |
sb/intel/lynxpoint: Use spaces around `|`
Coding style says so.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I72386bbe4b38602a641bf8dc9448d6a3e95d297a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46718
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/early_pch.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 6a5dd40644..03191d1c9a 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -43,7 +43,7 @@ static void pch_enable_bars(void) /* Enable ACPI BAR */ pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); /* Enable GPIO functionality. */ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |