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authorAngel Pons <th3fanbus@gmail.com>2020-10-24 23:00:34 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-11-02 10:40:50 +0000
commit90cdf705aa36f51a997c9bf81cf40ae159b3ce46 (patch)
treedd56bca2c3bae581b62548e415a966e658ddd152 /src/southbridge/intel/lynxpoint/bootblock.c
parent4fe4661d4e930bf6a3902136da48eb6b1683b4b3 (diff)
sb/intel/lynxpoint: Align with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46726 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/bootblock.c')
-rw-r--r--src/southbridge/intel/lynxpoint/bootblock.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index d142d3e6b7..802c58ef88 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -7,9 +7,7 @@
static void map_rcba(void)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
-
- pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+ pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
}
static void enable_port80_on_lpc(void)