diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-03-08 16:34:33 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-21 23:09:49 +0100 |
| commit | 7922b468b51eea58c7238f11b21820b8d3747d6b (patch) | |
| tree | a3675447a57e122c3987beb4c513f0c11876268e /src/southbridge/intel/lynxpoint/acpi/pch.asl | |
| parent | f5966b14e8d2a0613d5cbafbf73d76bed371899d (diff) | |
lynxpoint: Fix GPIO and PM base reservations
The kernel ACPI was not happy with the Add inside a
ResourceTemplate (or perhaps within the IO declaration)
Instead make a buffer of IO reservations and turn _CRS
into a method that updates the buffer depending on the
chipset type.
This adds an \ISLP() method that checks the chipset LPC
device ID to see if it is -LP or -H.
It also increases the PM base reservation to 256 bytes
and moves both GPIO and PM base to above 0x1000 on -LP
chipsets.
Change-Id: I747b658588a4d8ed15a0134009a7c0d74b3916ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2815
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/acpi/pch.asl')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/pch.asl | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 8632ad849e..ce8f0e0e81 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -23,6 +23,16 @@ Scope(\) { + // Return TRUE if chipset is LynxPoint-LP + Method (ISLP, 0, NotSerialized) + { + If (LEqual (\_SB.PCI0.LPCB.DIDH, 0x9c)) { + Return (1) + } else { + Return (0) + } + } + // IO-Trap at 0x800. This is the ACPI->SMI communication interface. OperationRegion(IO_T, SystemIO, 0x800, 0x10) @@ -33,7 +43,7 @@ Scope(\) } // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) - OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) + OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0xff) Field(PMIO, ByteAcc, NoLock, Preserve) { Offset(0x20), // GPE0_STS |