diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-05-24 11:10:31 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-25 23:45:23 +0100 |
| commit | 14031db21f3a41966a30bfc27bc97ddf03f40458 (patch) | |
| tree | 25604c15ca0046f639b3fbaa2eced064b2c224c8 /src/southbridge/intel/lynxpoint/acpi/lpc.asl | |
| parent | 96f77bd0d9436eb4259d2a132670735ac20e8b95 (diff) | |
lynxpoint: Add ACPI Method to enable GPIO as wake source
This is an LPT-LP specific method that will enable a specific
GPIO as an ACPI SCI wake source.
It can be used by a device _DSW method to enable a pin that is
otherwise not configured to generate SCI at runtime.
It will set:
- GPIO owner to ACPI
- GPIO route to SCI
- GPIO config to GPIO, Input, Inverted
Also clean up and remove ACPI field definitions that are unused
and/or incorrect.
Change-Id: I14acc2de50e6200f61c2898a7bd1252400e0f0be
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56621
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4189
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/acpi/lpc.asl')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/lpc.asl | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 7e2692637a..07b3fcf745 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -32,6 +32,8 @@ Device (LPCB) DIDH, 8, // Device ID High Byte Offset (0x40), PMBS, 16, // PMBASE + Offset (0x48), + GPBS, 16, // GPIOBASE Offset (0x60), // Interrupt Routing Registers PRTA, 8, PRTB, 8, @@ -47,24 +49,6 @@ Device (LPCB) IOD0, 8, IOD1, 8, - Offset (0xb8), // GPIO Routing Control - GR00, 2, - GR01, 2, - GR02, 2, - GR03, 2, - GR04, 2, - GR05, 2, - GR06, 2, - GR07, 2, - GR08, 2, - GR09, 2, - GR10, 2, - GR11, 2, - GR12, 2, - GR13, 2, - GR14, 2, - GR15, 2, - Offset (0xf0), // RCBA RCEN, 1, , 13, |