diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-24 18:03:18 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-14 08:37:36 +0000 |
| commit | 2aaf7c0a1d1a895805772fe5f878606161c8d3c5 (patch) | |
| tree | 5d590e1379ec8098b6a8040a5357075d309f86c9 /src/southbridge/intel/lynxpoint/acpi/globalnvs.asl | |
| parent | 2ead36334050ac692e64adc59a97320d8792adcc (diff) | |
haswell/lynxpoint: Align cosmetics with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45698
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/acpi/globalnvs.asl')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/globalnvs.asl | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 16c4b75f96..ee2d8000bc 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -2,9 +2,10 @@ /* Global Variables */ -Name(\PICM, 0) // IOAPIC/8259 +Name (\PICM, 0) // IOAPIC/8259 -/* Global ACPI memory region. This region is used for passing information +/* + * Global ACPI memory region. This region is used for passing information * between coreboot (aka "the system bios"), ACPI, and the SMI handler. * Since we don't know where this will end up in memory at ACPI compile time, * we have to fix it up in coreboot's ACPI creation phase. @@ -31,9 +32,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PWRS, 8, // 0x10 - Power State (AC = 1) /* Thermal policy */ Offset (0x11), - TLVL, 8, // 0x11 - Throttle Level Limit + TLVL, 8, // 0x11 - Throttle Level Limit FLVL, 8, // 0x12 - Current FAN Level - TCRT, 8, // 0x13 - Critical Threshold + TCRT, 8, // 0x13 - Critical Threshold TPSV, 8, // 0x14 - Passive Threshold TMAX, 8, // 0x15 - CPU Tj_max F0OF, 8, // 0x16 - FAN 0 OFF Threshold @@ -51,7 +52,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) F4OF, 8, // 0x22 - FAN 4 OFF Threshold F4ON, 8, // 0x23 - FAN 4 ON Threshold F4PW, 8, // 0x24 - FAN 4 PWM value - TMPS, 8, // 0x25 - Temperature Sensor ID + TMPS, 8, // 0x25 - Temperature Sensor ID /* Processor Identification */ Offset (0x28), APIC, 8, // 0x28 - APIC Enabled by coreboot |