diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-05-29 15:27:55 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-25 23:55:15 +0100 |
| commit | 2d9d39a7041cf531246845194f76cb9f65eaa08d (patch) | |
| tree | 51f60a7d9ede4ee6f2b44e270d85a08195dd6aef /src/southbridge/intel/lynxpoint/Makefile.inc | |
| parent | 5afca1357fdaebc5c4ad2b2a963f3c239648ba76 (diff) | |
lynxpoint: Enable USB clock gating, late setup, and sleep prep
Both EHCI and XHCI controllers have additional setup steps
that are not part of the PEI reference code so they need to
be done later.
Both controllers also have specific clock gating setup
requirements that are now implemented.
Additionally they both have specific requirements when entering
sleep states. XHCI needs something in S3/S4/S5 and EHCI only
has steps for S4/S5 entry.
Change-Id: Ic62cbc8b6255455e56b72dd5d52e27a311999330
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/57033
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4217
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 370e017fd5..4d96edfd5f 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -30,6 +30,7 @@ ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sata.c ramstage-y += usb_ehci.c +ramstage-y += usb_xhci.c ramstage-y += me_9.x.c ramstage-y += smbus.c ramstage-$(CONFIG_INTEL_LYNXPOINT_LP) += serialio.c |