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authorWerner Zeh <werner.zeh@siemens.com>2022-02-10 15:53:31 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-02-12 17:24:25 +0000
commitbc13c64a2d6821ad73c4481e30b92c39c30d027a (patch)
tree528f6c4dd4e32f2e477f4701b59a4aa8ab055bb3 /src/southbridge/intel/ibexpeak
parentc5b912f788765560c1db08f3341826b9c548b865 (diff)
mb/siemens/mc_apl{2,4,5,6}: Enable recovery MRC cache
The mainboards mc_apl{2,4,5,6} use VBOOT for verification and can be in a recovery state for different reasons. In this case we still want the MRC cache to be around to avoid the DRAM retraining on every boot. This patch enables the Kconfig switch HAS_RECOVERY_MRC_CACHE which makes the already available MRC recovery region in FMAP useable. Test=Boot mc_apl2 in recovery mode and make sure the recovery MRC cache is used. Change-Id: I2ea4993f05dd87a0e637f55e84b4fc06f5e29ecc Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Diffstat (limited to 'src/southbridge/intel/ibexpeak')
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