summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/ibexpeak
diff options
context:
space:
mode:
authorTristan Corrick <tristan@corrick.kiwi>2018-11-30 22:53:50 +1300
committerPatrick Georgi <pgeorgi@google.com>2018-12-03 13:14:06 +0000
commit63626b1a4a31588995ff6f0ba42952b6086cbded (patch)
tree968555763c26df36af3e64b7322b3c68d6c19913 /src/southbridge/intel/ibexpeak
parent32ceed8f269e48d9d500ee2ec9ba5b3f4435285e (diff)
sb/intel/common: Create a common PCH finalise implementation
The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak. Lynx Point now benefits from being able to write-protect the flash chip. For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done in bd82x6x. Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is configured, flashrom reports all flash regions as read-only, and does not manage to alter the contents of the flash chip. Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to work as before. Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/ibexpeak')
-rw-r--r--src/southbridge/intel/ibexpeak/Kconfig1
-rw-r--r--src/southbridge/intel/ibexpeak/Makefile.inc2
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h4
3 files changed, 2 insertions, 5 deletions
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index fe6526dc88..7e2254e4d1 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -28,6 +28,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SOUTHBRIDGE_INTEL_COMMON
+ select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index 906652d565..5c890300a4 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -37,7 +37,7 @@ ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c
ramstage-y += madt.c
ramstage-y += smi.c
-smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c
+smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c
romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c
romstage-y += ../bd82x6x/early_rcba.c
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 55478b908c..35bf0caced 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -51,10 +51,6 @@
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
-#if defined(__SMM__) && !defined(__ASSEMBLER__)
-void intel_pch_finalize_smm(void);
-#endif
-
#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
#if !defined(__SIMPLE_DEVICE__)