summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/ibexpeak
diff options
context:
space:
mode:
authorPatrick Rudolph <patrick.rudolph@9elements.com>2018-07-27 09:49:14 +0200
committerFelix Held <felix-coreboot@felixheld.de>2018-07-28 15:24:13 +0000
commit2a7be5bf3061fe8ccd5505f08489ea4671b61f20 (patch)
tree4a5bddfb5ed7bdecc8136f4d03e97d577c2f6fcd /src/southbridge/intel/ibexpeak
parent030ba1bff3bbf7210fc16fcd4fdd87f597e5bfa7 (diff)
sb/intel/gpio: Cache gpiobase in ramstage and romstage
Implement caching like it's done with pmbase. Change-Id: I26d56a9ff1a8d6e64c164f36e23b846b8b459380 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27664 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/ibexpeak')
0 files changed, 0 insertions, 0 deletions