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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-21 18:35:37 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-10-01 01:54:08 +0000 |
| commit | df128a55b183d3d7a6d7ae986f33abffac50f371 (patch) | |
| tree | 66f2cef1c9f2516da2783cb945b99f8223e74046 /src/southbridge/intel/ibexpeak | |
| parent | a84a7340b6291e209db2d5a3a28507816eec2223 (diff) | |
intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL
This is a PCI standard register, no need to alias its
definitions under different names.
Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/ibexpeak')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index e7cc9d2c7c..f7b29291db 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -82,10 +82,6 @@ void pch_enable(struct device *dev); #define SMLT 0x1b #define SECSTS 0x1e #define INTR 0x3c -#define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) |