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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-11-11 17:22:23 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-02-23 21:34:55 +0100
commit780935687d74f89a25a9c58952314be6af61c348 (patch)
tree193897842085f03675cb6b97e1f9ca523abb7a83 /src/southbridge/intel/ibexpeak
parent8c190f3518d504d904692e93e7881c379b89f542 (diff)
pcengines/apu1: Implement board GPIOs
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4. As our PCI subsystem currently does not configure PCI bridges that are marked disabled, but remain visible in the hardware, we cannot mark 0:14.4 disabled in devicetree just yet. Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8326 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge/intel/ibexpeak')
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