ACPI: Select ACPI_SOC_NVS only where suitable

Having some symmetry with <soc/nvs.h> now allows to reduce
the amount of gluelogic to determine the size and cbmc field
of struct global_nvs.

Since GNVS creation is now controlled by ACPI_SOC_NVS,
drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne
cannot have this selected until <soc/nvs.h> exists.

Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao

5 files changed, 5 insertions, 8 deletions

diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index c54c7e4d6c..cea0efed97 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -8,6 +8,7 @@ if SOUTHBRIDGE_INTEL_IBEXPEAK
 config SOUTH_BRIDGE_OPTIONS # dummy
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+	select ACPI_SOC_NVS
 	select AZALIA_PLUGIN_SUPPORT
 	select IOAPIC
 	select HAVE_SMI_HANDLER
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index 277f686ba9..643687f0c8 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -36,4 +36,6 @@ romstage-y += ../bd82x6x/early_rcba.c
 romstage-y += early_cir.c
 romstage-y += early_usb.c
 
+CPPFLAGS_common += -I$(src)/southbridge/intel/ibexpeak/include
+
 endif
diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
index bc18c2584d..bc18c2584d 100644
--- a/src/southbridge/intel/ibexpeak/nvs.h
+++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 2a612ba517..9bc8e6be30 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -20,10 +20,10 @@
 #include <cpu/x86/smm.h>
 #include "chip.h"
 #include "pch.h"
-#include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
 #include <southbridge/intel/common/spi.h>
+#include <soc/nvs.h>
 
 #define NMI_OFF	0
 
@@ -541,11 +541,6 @@ static void pch_lpc_enable(struct device *dev)
 	pch_enable(dev);
 }
 
-size_t gnvs_size_of_array(void)
-{
-	return sizeof(struct global_nvs);
-}
-
 void soc_fill_gnvs(struct global_nvs *gnvs)
 {
 	gnvs->apic = 1;
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index e83a9de2fb..41f92b5fa0 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -8,13 +8,12 @@
 #include <cpu/x86/smm.h>
 #include <cpu/intel/em64t101_save_state.h>
 #include <cpu/intel/model_2065x/model_2065x.h>
+#include <soc/nvs.h>
 #include <southbridge/intel/common/finalize.h>
 #include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/ibexpeak/me.h>
 #include "pch.h"
 
-#include "nvs.h"
-
 /* We are using PCIe accesses for now
  *  1. the chipset can do it
  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind