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authorPatrick Rudolph <siro@das-labor.org>2019-11-29 19:27:37 +0100
committerPatrick Rudolph <siro@das-labor.org>2020-09-26 17:31:08 +0000
commit819c2067424fb49347b38fc2a45ab0ad74b93f31 (patch)
tree799ecb49096c8fc8c4aa976208babd7401744d81 /src/southbridge/intel/ibexpeak/sata.c
parenta32df26ec0759bbac2080f6d9a437320f5d61157 (diff)
ironlake: Fix compilation on x86_64
Use correct datasize to compile on x86_64. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I213b2b1c5de174b5c14b67d1b437d19c656d13fd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/sata.c')
-rw-r--r--src/southbridge/intel/ibexpeak/sata.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 21371495eb..d1485707f3 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -90,7 +90,7 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x98, 0x00590200);
/* Initialize AHCI memory-mapped space */
- abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ abar = (u32 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);