diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2022-02-14 13:04:34 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-24 01:18:03 +0000 |
| commit | e2531ffaa87be5c26005ff986db8492a03f809e3 (patch) | |
| tree | 843fb04a1551f4b5173aefbd9ad31e93eeead96c /src/southbridge/intel/ibexpeak/pch.h | |
| parent | fdb0294846cf18b1077e8b0a4b2fe29d6b5a0bb4 (diff) | |
nb/intel/ironlake: Move out HECI remainders into southbridge
Move the remaining HECI-related stuff to southbridge scope, as the HECI
hardware is in the southbridge. Note that HECI BAR is now enabled a bit
earlier than before, but this shouldn't matter.
Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/pch.h')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 6565cd11f0..83e86c266c 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -22,6 +22,7 @@ /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 +#define DEFAULT_HECIBAR ((u8 *)0xfed17000) #include <southbridge/intel/common/rcba.h> |