diff options
| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/southbridge/intel/ibexpeak/lpc.c | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/ibexpeak/lpc.c')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/lpc.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 212471136d..db73b0add8 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -59,16 +59,16 @@ static void pch_enable_ioapic(struct device *dev) /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(IO_APIC_ADDR, 0x01); + set_ioapic_id(VIO_APIC_VADDR, 0x01); /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read(IO_APIC_ADDR, 0x01); - io_apic_write(IO_APIC_ADDR, 0x01, reg32); + reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x01, reg32); /* * Select Boot Configuration register (0x03) and * use Processor System Bus (0x01) to deliver interrupts. */ - io_apic_write(IO_APIC_ADDR, 0x03, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void pch_enable_serial_irqs(struct device *dev) @@ -394,7 +394,7 @@ static void enable_hpet(void) reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; - write32(0xfed00010, read32(0xfed00010) | 1); + write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); } static void enable_clock_gating(device_t dev) |