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authorArthur Heymans <arthur@aheymans.xyz>2019-05-28 13:39:20 +0200
committerMartin Roth <martinroth@google.com>2019-07-08 14:54:13 +0000
commitaadd1d0eaf860c6b503f4f10e17ea0abec6a9939 (patch)
tree019ddf5b904d86b65186306ee98ef7cdbc7c731d /src/southbridge/intel/ibexpeak/lpc.c
parentb429c5be15dd4263e8ddb599e1e1f15dd95c3bf0 (diff)
sb/intel/ibexpeak: Use common final SPI OPs setup
This also removes the relevant RCBA replays the mainboard dir. Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/lpc.c')
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index e7162b1e04..fa1ca92d78 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -38,6 +38,7 @@
#include "nvs.h"
#include <southbridge/intel/common/pciehp.h>
#include <southbridge/intel/common/acpi_pirq_gen.h>
+#include <southbridge/intel/common/spi.h>
#define NMI_OFF 0
@@ -785,6 +786,8 @@ static void southbridge_fill_ssdt(struct device *device)
static void lpc_final(struct device *dev)
{
+ spi_finalize_ops();
+
/* Call SMM finalize() handlers before resume */
if (CONFIG(HAVE_SMI_HANDLER)) {
if (CONFIG(INTEL_CHIPSET_LOCKDOWN) ||