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authorAngel Pons <th3fanbus@gmail.com>2020-10-17 18:39:04 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-10-20 11:52:16 +0000
commit77f340a707a868d56d8348cd9ab03308f4902bd9 (patch)
tree4906d0179f5f12309510cd184c6615a3f2d09073 /src/southbridge/intel/ibexpeak/early_usb.c
parente26e9b556deb86564b5f1cfe70e2095a03c964dc (diff)
sb/intel/ibexpeak: Align to coreboot's coding style
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I30512ef7ff7eb091e1f880c43a0a9ecf8625a710 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46530 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/early_usb.c')
-rw-r--r--src/southbridge/intel/ibexpeak/early_usb.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/src/southbridge/intel/ibexpeak/early_usb.c b/src/southbridge/intel/ibexpeak/early_usb.c
index 8957bfe404..e76ef7e8a1 100644
--- a/src/southbridge/intel/ibexpeak/early_usb.c
+++ b/src/southbridge/intel/ibexpeak/early_usb.c
@@ -35,21 +35,24 @@ void early_usb_init(const struct southbridge_usb_port *portmap)
RCBA32(0x3598) = 0;
reg32 = 0;
- for (i = 0; i < TOTAL_USB_PORTS; i++)
+ for (i = 0; i < TOTAL_USB_PORTS; i++) {
if (!portmap[i].enabled)
reg32 |= (1 << i);
+ }
RCBA32(USBPDO) = reg32;
reg32 = 0;
/* The OC pins of the first 8 USB ports are mapped in USBOCM1 */
- for (i = 0; i < 8; i++)
+ for (i = 0; i < 8; i++) {
if (portmap[i].enabled && portmap[i].oc_pin >= 0)
reg32 |= (1 << (i + 8 * portmap[i].oc_pin));
+ }
RCBA32(USBOCM1) = reg32;
reg32 = 0;
/* The OC pins of the remainder 6 USB ports are mapped in USBOCM2 */
- for (i = 8; i < TOTAL_USB_PORTS; i++)
+ for (i = 8; i < TOTAL_USB_PORTS; i++) {
if (portmap[i].enabled && portmap[i].oc_pin >= 4)
reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4)));
+ }
RCBA32(USBOCM2) = reg32;
/* Relock registers. */