diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-02-19 22:02:51 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-02-20 14:04:19 +0100 |
| commit | 2bebc8016630b2db5c0740041bf1cfc80e2706cd (patch) | |
| tree | 9746d2cf178dba3131cea37507acda794deb2620 /src/southbridge/intel/ibexpeak/early_thermal.c | |
| parent | 10b3974811b7e851856f71f8e09e8c5c682326f6 (diff) | |
ibexpeak/thermal: set temperature target in early init.
Properly determine temperature target and set it in early
init rather than hardcoding it in late init.
Change-Id: Ie763f205890674a9dd1d9c5974caaccdd67cea14
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5264
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/early_thermal.c')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/early_thermal.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index 9d96a34877..d23749e513 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -20,12 +20,15 @@ #include <arch/io.h> #include "pch.h" +#include "cpu/intel/model_2065x/model_2065x.h" +#include <cpu/x86/msr.h> /* Early thermal init, must be done prior to giving ME its memory which is done at the end of raminit. */ void early_thermal_init(void) { device_t dev; + msr_t msr; dev = PCI_DEV(0x0, 0x1f, 0x6); @@ -38,6 +41,12 @@ void early_thermal_init(void) pci_read_config32(dev, 0x40) | 5); /* Perform init. */ + /* Configure TJmax. */ + msr = rdmsr(MSR_TEMPERATURE_TARGET); + write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6); + /* Northbridge temperature slope and offset. */ + write16(0x40000016, 0x7746); + /* Enable thermal data reporting, processor, PCH and northbridge. */ write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0); /* Disable temporary BAR. */ |