diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-25 00:23:20 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-24 14:03:54 +0000 |
| commit | 72f4dda6b7d1de5eef1df1d32be4595067c4a15d (patch) | |
| tree | baaeb4f0353831bead527ff08cfd83e58814bd14 /src/southbridge/intel/ibexpeak/chip.h | |
| parent | d3318cfe498bf53d8ce7d1cd55afad4a93705216 (diff) | |
sb/intel/lynxpoint/pcie: Fix clock gating routine
The use of `1 < 5` as a bit mask was obviously a typo. Correct it as
`1 << 5` to match what Intel doc #493816 (Lynx Point PCH BWG) states.
Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45713
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/chip.h')
0 files changed, 0 insertions, 0 deletions