summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/ibexpeak/Makefile.inc
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2019-10-02 00:21:01 +0200
committerArthur Heymans <arthur@aheymans.xyz>2019-10-06 10:13:21 +0000
commitd0310faa3bc4d3b62d17d632fbaee98c146eebe0 (patch)
tree8d3a55eb4135484ae7729f8092876ba36c165a2e /src/southbridge/intel/ibexpeak/Makefile.inc
parentf266dc61743cfce56ea026e66bc88cad8e5de2bb (diff)
sb/intel/ibexpeak: Implement PCH function disable in chip_ops
This does the following: - implement a PCH disable function that will be called by the PCI drivers as part of their chip_ops - removes the iobp_x calls as those don't exist on ibexpeak - complete the devicetree with to be disabled PCI devices for the chip_ops to be called - Clean up some code copied from bd82x6x Change-Id: I78d25ffe9af482c77d397a9fdb4f0127e40baddc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/Makefile.inc')
-rw-r--r--src/southbridge/intel/ibexpeak/Makefile.inc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index 97565d6bec..9caf29fd87 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -15,7 +15,7 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y)
-ramstage-y += ../bd82x6x/pch.c
+ramstage-y += pch.c
ramstage-y += azalia.c
ramstage-y += lpc.c
ramstage-y += ../bd82x6x/pci.c
@@ -35,7 +35,7 @@ ramstage-y += ../bd82x6x/me_status.c
ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c
ramstage-y += madt.c
-smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c
+smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c
romstage-y += early_smbus.c
romstage-y +=../bd82x6x/early_me.c