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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-06-13 00:13:50 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-06-13 00:27:07 +0200 |
| commit | 3a09179f462ad3f6111c7b8ebbad7d78534f9234 (patch) | |
| tree | b854e11a926e555a4ade85950846b8cdea0ce56b /src/southbridge/intel/ibexpeak/Kconfig | |
| parent | 0210119b4b95e84f954cfd6dc11aafbc187421af (diff) | |
Revert "Add support for Intel Ibex Peak (Mobile 5) southbridge"
This reverts commit 0210119b4b95e84f954cfd6dc11aafbc187421af
Change-Id: I5be3f2a54394c592650a0dcd671e4a72ae796cb2
Reviewed-on: http://review.coreboot.org/3443
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/Kconfig')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/Kconfig | 85 |
1 files changed, 0 insertions, 85 deletions
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig deleted file mode 100644 index 810e4c2c59..0000000000 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ /dev/null @@ -1,85 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -config SOUTHBRIDGE_INTEL_IBEXPEAK - bool - -if SOUTHBRIDGE_INTEL_IBEXPEAK - -config SOUTH_BRIDGE_OPTIONS # dummy - def_bool y - select IOAPIC - select HAVE_HARD_RESET - select HAVE_USBDEBUG - select HAVE_SMI_HANDLER - select USE_WATCHDOG_ON_BOOT - select PCIEXP_ASPM - select PCIEXP_COMMON_CLOCK - select SPI_FLASH - -config EHCI_BAR - hex - default 0xfef00000 - -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/ibexpeak/bootblock.c" - -config SERIRQ_CONTINUOUS_MODE - bool - default n - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - -config HPET_MIN_TICKS - hex - default 0x80 - -config HAVE_GBE_BIN - bool "Add gigabit ethernet firmware" - default n - help - The integrated gigabit ethernet controller needs a firmware file. - Select this if you are going to use the PCH integrated controller - and have the firmware. - -config GBE_BIN_PATH - string "Path to gigabit ethernet firmware" - depends on HAVE_GBE_BIN - default "3rdparty/mainboard/$(MAINBOARDDIR)/gbe.bin" - -config LOCK_MANAGEMENT_ENGINE - bool "Lock Management Engine section" - default n - help - The Intel Management Engine supports preventing write accesses - from the host to the Management Engine section in the firmware - descriptor. If the ME section is locked, it can only be overwritten - with an external SPI flash programmer. You will want this if you - want to increase security of your ROM image once you are sure - that the ME firmware is no longer going to change. - - If unsure, say N. - -endif |