src/southbridge: Code formating

Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)

3 files changed, 68 insertions, 69 deletions

diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index 6a0f0d222f..a02a2afde6 100644
--- a/src/southbridge/intel/i82870/ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
@@ -11,11 +11,10 @@ static int num_p64h2_ioapics = 0;
 
 static void p64h2_ioapic_enable(device_t dev)
 {
-    /* We have to enable MEM and Bus Master for IOAPIC */
-    uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	/* We have to enable MEM and Bus Master for IOAPIC */
+	uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 
-
-    pci_write_config16(dev, PCI_COMMAND, command);
+	pci_write_config16(dev, PCI_COMMAND, command);
 }
 
 /**
@@ -29,70 +28,70 @@ static void p64h2_ioapic_enable(device_t dev)
  */
 static void p64h2_ioapic_init(device_t dev)
 {
-    uint32_t memoryBase;
-    int apic_index, apic_id;
+	uint32_t memoryBase;
+	int apic_index, apic_id;
 
-    volatile uint32_t* pIndexRegister;    /* io apic io memory space command address */
-    volatile uint32_t* pWindowRegister;    /* io apic io memory space data address */
+	volatile uint32_t* pIndexRegister;    /* io apic io memory space command address */
+	volatile uint32_t* pWindowRegister;    /* io apic io memory space data address */
 
-    apic_index = num_p64h2_ioapics;
-    num_p64h2_ioapics++;
+	apic_index = num_p64h2_ioapics;
+	num_p64h2_ioapics++;
 
-    // A note on IOAPIC addresses:
-    //  0 and 1 are used for the local APICs of the dual virtual
-    //  (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
-    //  6 and 7 are used for the local APICs of the dual virtual
-    //  (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
-    //  2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
+	// A note on IOAPIC addresses:
+	//  0 and 1 are used for the local APICs of the dual virtual
+	//  (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
+	//  6 and 7 are used for the local APICs of the dual virtual
+	//  (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
+	//  2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
 
-    // Map APIC index into APIC ID
-    // IDs 3, 4, 5, and 8+ are available (see above note)
+	// Map APIC index into APIC ID
+	// IDs 3, 4, 5, and 8+ are available (see above note)
 
-    if (apic_index < 3)
-        apic_id = apic_index + 3;
-    else
-        apic_id = apic_index + 5;
+	if (apic_index < 3)
+		apic_id = apic_index + 3;
+	else
+		apic_id = apic_index + 5;
 
-    ASSERT(apic_id < 16);       // ID is only 4 bits
+	ASSERT(apic_id < 16);       // ID is only 4 bits
 
-    // Read the MBAR address for setting up the IOAPIC in memory space
-    // NOTE: this address was assigned during enumeration of the bus
+	// Read the MBAR address for setting up the IOAPIC in memory space
+	// NOTE: this address was assigned during enumeration of the bus
 
-    memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-    pIndexRegister  = (volatile uint32_t*) memoryBase;
-    pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
+	memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+	pIndexRegister  = (volatile uint32_t*) memoryBase;
+	pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
 
-    printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x  MBAR = %p DataAddr = %p\n",
-                 apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
-                 PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
+	printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x  MBAR = %p DataAddr = %p\n",
+		apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
+		PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
 
-    apic_id <<= 24;             // Convert ID to bitmask
+	apic_id <<= 24;             // Convert ID to bitmask
 
-    *pIndexRegister = 0;        // Select APIC ID register
-    *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id;   // Set the ID
+	*pIndexRegister = 0;        // Select APIC ID register
+	*pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id;   // Set the ID
 
-    if ((*pWindowRegister & (0xF<<24)) != apic_id)
-        die("p64h2_ioapic_init failed");
+	if ((*pWindowRegister & (0xF<<24)) != apic_id)
+		die("p64h2_ioapic_init failed");
 
-    *pIndexRegister  = 3;   // Select Boot Configuration register
-    *pWindowRegister |= 1;  // Use Processor System Bus to deliver interrupts
+	*pIndexRegister  = 3;   // Select Boot Configuration register
+	*pWindowRegister |= 1;  // Use Processor System Bus to deliver interrupts
 
-    if (!(*pWindowRegister & 1))
-        die("p64h2_ioapic_init failed");
+	if (!(*pWindowRegister & 1))
+		die("p64h2_ioapic_init failed");
 }
 
 static struct device_operations ioapic_ops = {
-        .read_resources   = pci_dev_read_resources,
-        .set_resources    = pci_dev_set_resources,
-        .enable_resources = pci_dev_enable_resources,
-        .init     = p64h2_ioapic_init,
-        .scan_bus = 0,
-        .enable   = p64h2_ioapic_enable,
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init     = p64h2_ioapic_init,
+	.scan_bus = 0,
+	.enable   = p64h2_ioapic_enable,
 };
 
 static const struct pci_driver ioapic_driver __pci_driver = {
-        .ops    = &ioapic_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = PCI_DEVICE_ID_INTEL_82870_1E0,
+	.ops    = &ioapic_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82870_1E0,
 
 };
diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c
index 71d2c538e9..b886c5244f 100644
--- a/src/southbridge/intel/i82870/pci_parity.c
+++ b/src/southbridge/intel/i82870/pci_parity.c
@@ -5,19 +5,19 @@
 
 void p64h2_pci_parity_enable(void)
 {
-        uint8_t reg;
+	uint8_t reg;
 
-        /* 2SERREN - SERR enable for PCI bridge secondary device  */
-        /* 2PEREN  - Parity error for PCI bridge secondary device  */
-        pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg);
-        reg |= ((1 << 1) + (1 << 0));
-        pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
+	/* 2SERREN - SERR enable for PCI bridge secondary device  */
+	/* 2PEREN  - Parity error for PCI bridge secondary device  */
+	pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg);
+	reg |= ((1 << 1) + (1 << 0));
+	pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
 
-        /* 2SERREN - SERR enable for PCI bridge secondary device  */
-        /* 2PEREN  - Parity error for PCI bridge secondary device  */
-        pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg);
-        reg |= ((1 << 1) + (1 << 0));
-        pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
+	/* 2SERREN - SERR enable for PCI bridge secondary device  */
+	/* 2PEREN  - Parity error for PCI bridge secondary device  */
+	pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg);
+	reg |= ((1 << 1) + (1 << 0));
+	pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
 
-        return;
+	return;
 }
diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c
index b46b3381ab..e8d890ab95 100644
--- a/src/southbridge/intel/i82870/pcibridge.c
+++ b/src/southbridge/intel/i82870/pcibridge.c
@@ -23,16 +23,16 @@ static void p64h2_pcix_init(device_t dev)
 
 }
 static struct device_operations pcix_ops  = {
-        .read_resources   = pci_bus_read_resources,
-        .set_resources    = pci_dev_set_resources,
-        .enable_resources = pci_bus_enable_resources,
-        .init             = p64h2_pcix_init,
-        .scan_bus         = pci_scan_bridge,
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = p64h2_pcix_init,
+	.scan_bus         = pci_scan_bridge,
 	.reset_bus        = pci_bus_reset,
 };
 
 static const struct pci_driver pcix_driver __pci_driver = {
-        .ops    = &pcix_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = PCI_DEVICE_ID_INTEL_82870_1F0,
+	.ops    = &pcix_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82870_1F0,
 };